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FMCOMMS-1 DAC Sample Rate

Question asked by jeffkt2 on Jun 5, 2015
Latest reply on Jun 5, 2015 by rejeesh

I'm trying to change the DAC sample rates on the FMCOMMS-1 and there's a couple things I don't quite understand. I'm using the no-os drivers, and I've modified the AD9523_cfg.h settings to allow for a 1024 MHz clock before any of the channel dividers:


pll2_ndiv_a_cnt = 1

pll2_ndiv_b_cnt = 6

pll2_freq_doubler_en = 0


VCO2 output: 122.88 x (4*6+1) = 3072 MHz

M1/M2 outputs: 3072 MHz / 3 = 1024 MHz


The 10 bit channel dividers should provide any frequency between 1 and 1024 MHz (in 1 MHz increments). I think there's some weird rounding that occurs, but it works fine for powers of two.


In the no-os example main.c, you should be able to change the rate by changing the defInit->dacSamplingRate. If I set the dacSamplingRate to 128MHz, everything works fine. If I try to set the dacSamplingRate to 64MHz, the output clocks I probe are correct, but the subsequence dactest() fails. I get the following error message:


dac_setup: status NOT set!!

dac_setup: dac_clock(63.995MHz)


Looks like its ready register 0x405c to determine status not set. Any ideas why? Thanks for the help!!



This is kind of a follow up question to this thread:

AD9122 clocking and sampling rate

In that thread, someone mentioned that trying 16MHz was probably too slow for the SERDES, but trying 64MHz in this case shouldn't be a problem?