My interest is in the AD7175-2 specifically, but the question applies to all delta-sigma ADCs. The data sheets don't specify the data rate used for the INL specifications; would it be the lowest (5 SPS)?

How does the AD7175-2's INL vary with data rate? Does the INL deteriorate, or improve (unlikely I guess) at higher speeds? Do all sigma-delta ADCs behave similarly in this regard or does the order/architecture have a big impact?

I had assumed that the data rate of delta-sigma ADCs is determined by the amount of oversampling and all done in the digital domain in the filtering/decimation rather than by varying the modulator rates. I also presumed that INL errors arise in the analogue stages and thus would be independent of the data rate, but now I'm not sure.

I ask because I want to do low speed, high resolution measurements but would prefer to sample at a higher rate of 1kSPS, or even 10k, and filter/average externally so that I also get the higher speed (but noisier) samples at the same time. Would the higher sampling rate negatively impact the INL and if so would the external filtering improve it?

If the filtering does impact the INL, what would be the best type of filter to use to minimize linearity errors?

Thanks,

Tony H

Hi Tony H,

Apologies for the delay. The specifications are base from the maximum output data rate. The INL is not impacted by the data rate. The INL is determined by the ADC core which always runs at the same modulator rate (8Mhz). The output data rate is changed by the digital filter increasing the number of samples used but it will have no effect on the modulator itself. The best case for the INL is to have a fully differential input with VDD1/2 common mode and use external reference.

Regards,

Jonathan