How valid Duty Cycle range for input clock AD9269?
The optimum SNR performance will be achieved with a nominal ~48-52% CLK duty cycle. The AD9269 ADC family includes an internal Duty Cycle Stabilizer (DCS) circuit that when enabled can accommodate a fairly wide range of Duty Cycle variations.
Please refer to the Clock Duty Cycle section on pg 23 of the datasheet and Fig 54 for more details.
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