I have be working with the AD9250-170 evalution board and KC705(xilinx FPGA evalution board) to test JESD204B interface,subclass 1 (I did not use xilinx JESD204B IP core) for about a month,now get some problems:
when I got the correct information in CGS Phase and ILAS Phase, I could not get any valid data in Data Transmission Phase,
First I thought maybe the value of regist 0x3A was wrong ,because every time I read it ,I got 0!
now I think the value of regist 0x3A is right.
Secnod I thought maybe the values of M,L,S,F and N' were not correct,but when I tried some other values and got the same result, I thought that was not the problem!
Now I am at my wit's end,can any guys give me some suggestion about the recommand value of all regists and other help?