AnsweredAssumed Answered

Data rate between AD9364 and KC705

Question asked by jinojs on Jun 3, 2015
Latest reply on Jun 5, 2015 by jinojs



I'm using KC705 and FMCOMMS4 boards and verifying the Tx and Rx paths.

I'm using external reference clock of 38.4MHz and have kept the same value in init param (reference_clk_rate).


Based on this clock, what are the other clock parameters that I need to modify in the No-OS reference code?


In the below table, which values should I need to modify for having the Rx data frequency of 38.4MHz?


/* Rate & BW Control */

{983040000, 245760000, 122880000, 61440000, 30720000, 30720000}, //uint32_t rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies

{983040000, 122880000, 122880000, 61440000, 30720000, 30720000}, //uint32_t tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies


With the default (above) settings, we see that the data received from ADI to FPGA is 76.8MHz. Is it as expected? Where can we control the data frequency between AD board and FPGA?

We have configured them in LVDS and FDD modes.


Please guide.


Thank you,