Is it possible to run a DDR2 device at DCLK=400 MHz, CCLK=450 MHz, SYSCLK=225Mz on ADSP-SC58x/ADSP-2158x processors?

Discussion created by Mitesh Employee on Jun 3, 2015

Yes, it is possible with the help of two CGUs available on ADSP-SC58x/ADSP-2158x devices. One CGU can be programmed to generate CCLK=450 MHz and SYSCTK=225 MHz and another CGU can be programmed to generate DCLK = 400 MHz. By default the DCLK uses the clock routed by CGU0, but CDU can be programmed to route the DCLK from CGU1 instead of CGU0. Make sure that the fabric is programmed in ASYNC mode (default mode) to support the asynchronous clock domain for DCLK.