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ADL5513 power-down timing for low VDD

Question asked by eike on Jun 3, 2015
Latest reply on Jul 10, 2015 by eike

Dear all,

I would like to use the ADL5513 near its minimum operating voltage of 2.7V in order to conserve power. The nominal value in my application is 2.8V. To further conserve power the device enabled and disabled periodically using the TADJ pin. TADJ is switched between VCC and GND by a high speed logic gate.

The ADL5513 datasheet specifies 80 ns for the "Enable Time" and 165 ns "Disable Time" for CLPF = 1 pF. When operating at 2.8 V a much longer "Enable Time" of approx. 350 ns can be observed while "Disable Time" is very close to the data sheet's specified value. I'm attaching a waveform showing TADJ and VOUT at 100 MHz and 0dBm for reference.


Is the observed behaviour correct, i.e. power-down becomes slower as VCC is lowered, or is there a way to reduce the "Enable Time" for relatively low operating voltages?


Best regards, thanks in advance,



PS: I believe that the "Pulse Response Time"  for CLPF = open, 500 us pulse width is not 5.5 us as specified in the datasheet on page 6 but closer to 20 ns, perhaps there's been a copy&paste error?