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How to change FPGA reference clock out   from 30 MHz  to 30.72 MHz  for AD-FMCOMMS1-EBZ

Question asked by amdakwar12 on Jun 3, 2015
Latest reply on Jun 10, 2015 by amdakwar12

Dear Sir/madam,


I need to change reference clock out  value from 30 MHz to 30.72 Mhz  for  AD-FMCOMMS1-EBZ.(i wish to change input reference clock for AD9548).

In given referencee design it was 30 MHz. But in My design I need 30.72MHz.

I am using Linux driver support.

Please suggest how to modify dts file of AD-FMCOMMS1-EBZ to make this change.