I want to integrate a CIC (I and Q) block to the reference design after axi_ad9361 and before util_adc_pack. Following are the details of the connections of CIC-I block:
1. s_axis_data_tdata[15:0] of CIC-I connects to adc_data_i0[15:0] of axi_ad9361
2. s_axis_data_tready of CIC-I connects to chan_enable_0 of util_adc_pack
3. s_axis_data_tvalid of CIC -I connects to adc_enable_i0 of axi_ad9361
4. aclk of CIC-I connects to clk of axi_ad9361
5. m_axis_data_tdata[15:0] of CIC-I connects to chan_data_0[15:0] of util_adc_pack
6. m_axis_data_tvalid of CIC-I connects to chan_valid_0 of util_adc_pack
1. s_axis_data_tdata[15:0] of CIC-Q connects to adc_data_q0[15:0] of axi_ad9361
2. s_axis_data_tready of CIC-Q connects to chan_enable_1 of util_adc_pack
3. s_axis_data_tvalid of CIC -Q connects to adc_enable_q0 of axi_ad9361
4. aclk of CIC-Q connects to clk of axi_ad9361
5. m_axis_data_tdata[15:0] of CIC-Q connects to chan_data_1[15:0] of util_adc_pack
6. m_axis_data_tvalid of CIC-Q connects to chan_valid_1 of util_adc_pack
I am not very certain about the way I am connecting (especially a_axis_data_tready and a_axis_data_tvalid) these blocks as it is functionally not correct, compiles fine though! I have also attached the specifications of CIC block for your kind reference.
Could you let me know if I am making any obvious mistakes in connecting these blocks please?
Any help appreciated!