I see in a previous topic (http://ez.analog.com/message/11288#11288) that if the power management modes are enabled while using JTAG, the part must be mass erased. This would seem to prevent using any core clock souce other than the internal oscillator PLL output, since in the description for the oscillator (p.49 in Rev0 of the ADuC7128/7129 datasheet), the datasheet provides sample code to put the part into nap mode while changing the clock source.
Is there a reliable way to switch the clock source without using nap mode? Does nap mode have to be used in the case where an external clock is used directly (without the PLL)? I also don't see any restriction on changing the CD bits. Can these be modified indiscriminately assuming the PLL is locked?
I'm also confused as to why the part needs to be mass erased. If my code has a problem and the core remains in a low power mode, I can certainly see the jtag not being able to take control of the core. But if the part is not currently in a low power mode and has a valid core clock, shouldn't the JTAG be able to take over the core?