Our customer will use ADXL362.
Customer asks below.
We do not know "what Datasheet P.19 description " means
Please let me know your advice.
We think that ADXL362 needs that CS goes low to high once for next command after one command.
If possible, customer would like to use ADXL362 without control of CS ( while CS is always low).
Datasheet P.19 says FIFO can sustain bursting at the SPI clock rate as long as SPI clock is faster than 1MHz.
Does above mean that burst is controlled by SPI clock rate without control of CS ?
For example, in the case that CS is always low, if we stop the input of SPI clock, is burst stopped ?
And if we input SPI clock after above, can we start next command while CS is always low ?
If there is any query, please let me know