ADuC7060/ADuC7061 Datasheet Rev.B:
FEESTA register bit 3 means: Flash interrupt status bit. Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the FEEMOD register is set. Cleared when reading the FEESTA register.
But ADuC706x has no FLASH interrupt source.
What is wrong with it?