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Use ADN2816 at the "lock to input data" mode

Question asked by tak on May 28, 2015
Latest reply on May 31, 2015 by tak

Hello all,

 

Could you let me know the following question for ADN2816?

At the "Lock to input data" mode as the resister (Reg Name: CTRLA, Address: 0x8, D0), it means reference clock does not use.

After lock to input data, If input signal is lost to "0" or "1" continuously, for example, disconnect the input (PIN, NIN) pins suddenly.

How does behave output-pins of the "DATAOUT", "CLKOUT" and "LOL", after input signal lost?

Is it same situation below or different?

 

I heard in the past, If use the "Lock to reference clock" mode, each output-pins behaves below.

     DATAOUT:  output the detection data of the input buffer as the noise

     CLKOUT:  output the clock (using reference clock)

     LOL:  Active (detect the lost)

 

Thank you very much,

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