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Where to insert our IP in the FMCOMMS2 Ref Imp?

Question asked by BrianUCSD on May 27, 2015
Latest reply on Jan 4, 2016 by ACozma


A primary market for the AD9361 is the software-defined radio market.  We are graduate students implementing a simple SDR waveform on a Zed Board with the FMCOMMS3 board as the SDR tx/rx, driven by data from the ARM running Linux.  We have studied the Analog Devices FMCOMMS wiki site and have synthesized the Analog Devices FMCOMMS2 reference project contained in the AD GitHub HDL repository. We cannot relate the 24 blocks contained in the Vivado block design to the high-level diagram shown in the high-level diagram shown in resources:eval:user-guides:ad-fmcomms2-ebz:cf_ad9361_zc706_bd.jpg [Analog Devices Wiki].  Although we have studied the Verilog code, it is quite low level  and with very few comments.  There is no documentation for the AD cores.  It would be a big help to the community, and possibly reduce the number of questions you field, if you can define them as part of your reply to the questions below. 



1. We are attempting to determine where within the reference implementation's 24 blocks would be the logical location for inserting our waveform blocks (e.g., symbol (de)mapper, pulse shaper, timing recovery, etc.).  Our sense is that the flow of Tx data (the Rx chain has a parallel form) is the following (see figure):


      1. sys_ps7 --> axi_ad9361_dac_dma (via the axi_ad9361_dac_dma_axi interface connection)
      2. axi_ad9361_dac_dma --> util_dac_unpack (via the fifo_data net)
      3. util_dac_unpack --> axi_ad9361 (via the axi_ad9361_dac_data_0-3 nets).


In addition to performing the waveform functions, our IP blocks will effectively perform the unpacking.  Therefore, my sense is that a likely approach would be


      1. Same as #1 above
      2. from the axi_ad9361_dac_dma block to our waveform block and finally
      3. from our waveform block to the axi_ad9361 block


2.  The list below are the IP cores within the FMCOMMS2-EBZ reference implementation contained in the AD GitHub HDL repository.  Can you provide a definition for each block in terms of the high-level diagram shown in the high-level diagram shown in resources:eval:user-guides:ad-fmcomms2-ebz:cf_ad9361_zc706_bd.jpg        [Analog Devices Wiki].



  1. util_adc_pack
  2. util_dac_unpack
  3. axi_ad9361_adc_dma
  4. axi_ad9361
  5. sys_rstgen
  6. ila_adc
  7. axi_cpu_interconnect
  8. axi_hdmi_dma
  9. axi_ad9361_dac_dma
  10. axi_hdmi_interconnect
  11. axi_i2s_adi
  12. axi_hdmi_core
  13. axi_hdmi_clkgen
  14. axi_iic_fmc
  15. sys_audio_clkgen
  16. sys_ps7
  17. axi_spdif_tx_core
  18. sys_logic_inv
  19. sys_wfifo_0
  20. sys_wfifo_1
  21. sys_wfifo_2
  22. sys_wfifo_3
  23. axi_iic_main
  24. sys_concat_intc