I see you support a wide variety of different output standards within your clock portfolio. What are the relative advantages and disadvantages for each of these:
LVPECL has the advantage of swing amplitude over LVDS (800mV versus 350mV).This produces a higher effective slew rate at a receiver and can result in lower jitter. LVPECL also allows the user to have a high drive current which helps drive highly capacitive loads and long trace lengths.
LVDS offers the advantages of lower power dissipation and simpler termination versus LVPECL. Like LVPECL, it has the advantage of being fully differential.
CMOS logic enjoys a large amplitude and ease of connection to may devices. However, the large voltage swing and lack of inherent impedance matching can easily lead to crosstalk and poor signal integrity.
The HSTL topology on ADI's newest parts offers low power, fast slew rate, low noise, and ease of termination. Its 800mV voltage swing is compatible with LVPECL receivers, and by AC-coupling HSTL, it can drive LVPECL receivers.
In order to properly drive a 3.3V LVPECL, the user should AC-couple using 0.1uF decoupling caps, and then use a Thevenin-equivalent termination with a 130 ohm pull-down and 82 ohm pull-up resistor on each leg of the differential pair.
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