I am trying to work through the instructions from MathWorks for getting their 'sdrzQPSKTxFPGA' model through their HDL Workflow Advisor.
Yesterday I downloaded MathWork's support package for the FMCOMMS1 RevB/C board. The support package is designed to support any combination of either the Xilinx ZC706 board or the AVNET Zed Board with either the FMCOMMS1 Rev B/C or the FMCOMMS2/3 board. I am using a Zed Board and an FMCOMMS1 Rev B board. Yesterday I installed this support package from Mathworks and proved via their example app that It works with my Zed/FMCOMMS1 configuration. Today I am trying to use the support package to generate HDL code for MathWorks 'sdrzQPSKTxFPGA' example ("Targeting HDL Optimized QPSK Transmitter with Analog Devices FMCOMMS 1"). For whatever reason, the Zed Board is not a choice from the HDL Workflow Advisor's "Target Platform" drop-down selection list; only the ZC706. Please refer to the HDL Workflow Advisor screenshot below. I therefore am unable to generate HDL code from Simulink and target the FMCOMMS1 in a way that, as I understand, will let me use the Simulink model with the Zed and FMCOMMS1 boards "in-the-loop".
Has anyone had a similar experience? If you have, do you know of a resolution? I realize this may be an issue with a MathWorks application, but this EngineerZone section seems to be where the FMCOMMS community of interest gathers.