I have seen multiple schemes for terminating LVPECL clock signals. What are the trade offs and special considerations for picking the optimal termination?
There are various practices for terminating LVPECL outputs. Some of these hark back to the old days of ECL, where both sides of the output were driving 50 ohm single-ended transmission lines. This resulted in the "standard" ECL termination being 50 ohms to a stiff power rail at (Vsh-2) volts. (Remember that for ECL, Vsh - the high rail - was ground, or zero volts; and the Vsl - the low rail - was -5.2 V.) Later on, since the requirement for a -2V power rail was a problem, users adopted the Thevenin equivalent form of that termination, which consists of a resistor divider between Vsh and Vsl. This is where the 130 ohm to Vsh and 82 ohm to Vsl divider. This is still terminating to the high rail minus 2V with 50 ohms.
The data sheets for the ADI clock ICs show both a load resistor with AC-coupled termination, and the "traditional" Thevenin termination scheme for LVPECL. There seems to be little difference between the two termination methods in jitter performance; layout and other considerations are more important. Both termination schemes are capable of giving the same jitter performance when all other factors are considered.
These days we recommend microstrip differential 100 ohm transmission lines to couple LVPECL outputs to their driven device inputs. This allows a somewhat different termination scheme. The resistors to ground on each output set the emitter current of the output drivers, and determine the output impedance of the drivers (re=1/gm=Vt/Ic). So, for the recommended 200 ohm resistors, the emitter current for a logic high output is (3.3 - 1)/200 = 11.5 mA and for a logic low output (3.3 - 1.8)/200 = 7.5 mA. Assuming a reasonable beta (>200), this gives Re(h) = Vt/Ic = 0.026/0.0115 = 2.26 ohms, and Re(l) = 0.026/0.0075 = 3.47 ohms. Therefore the differential output resistance = 5.73 ohms.
This relatively low differential output impedance drives a balanced, fully differential 100 ohm transmission line. The power transfer is not maximum, but the voltage swing is maintained at 800 mV differential. The far end (receiver end) is terminated in the transmission line characteristic impedance (100 ohms across the differential line) to minimize reflections in the reverse direction. Overall, this is a very good and clean termination scheme.
Now, if the near-end termination resistors are reduced below 200 ohms, the emitter current increases, and the signal fall time improves (because an emitter follower cannot "pull down" a node, it depends on the emitter resistor to discharge any capacitance on the node). But, the voltage swing does not change, and the receiver does not see any bigger signal. Also, it is important to keep the emitter current below the value set by the allowable current density in the output device. This is set by the design and process parameters, and is about 18 mA in the case of the AD951x parts. Therefore, it is not recommended to increase the LVPECL output current to a point where it may exceed 18 mA during a static (outputs not switching) output logic high (2.3 V) condition. This limits the LVPECL near-end resistor to no less than 128 ohms.
The reason for recommending 200 ohms for the LVPECL near-side terminations is: 1) it keeps the static current (output not switching) well within the allowable current density rating of the part; 2) it provides for a suitably low output impedance for the LVPECL driver.
So, our recommendation for the LVPECL near-end termination resistors to ground is for values between 150 and 200 ohms for reliability and overall performance.
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