I have seen figure of merit used to describe PLL's. I am curious what this measures and how it manifests itself in a PLL based clock.
Figure of merit in a PLL is the normalized phase noise floor of the phase detector. The unit of measurement is dBc/Hz. The phase detector noise floor is estimated by measuring the in-band noise at the VCO output and subtracting 20 log N (where N is the N divider value) and 10 log Fpfd (where Fpfd is the phase detector frequency). Normalized PN = PN tot - 10 log Fpfd - 20 log N.
Total close-in phase noise in a phase-locked loop (dB) can be expressed as follows:
PNtotal= PNsynth + 20logN + 10logFpdf
The PNsynth is often called the PLLs Figure of Merit or FOM. This provides a figure of merit for the PLL Synthesizer circuit itself, irrespective of the noise contributed by PLL N value and PFD frequency, since these would be the same for any similar circuit being compared.
Below is an example of a PLL with VCO operating at 3.932 GHz.
FOM = 219.
Feedback divider (or frequency multiplier) = 32.
Phase detector rate = 122.88MHz.
PN total = -220 + 20log(32) +10log(122.88MHz)
= (–220 + 30 + 81) dBc/Hz
= –109 dBc/Hz
Expect to see the PLL close in noise to be approximately -109dBc/Hz at the 3.9GHz output.
Thanks for the complete explanation
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