What are the key specifications I should look to on your clock parts if I am deciding which one to use to clock my high performance data converter?
As the ADC converter sample frequency and analog input frequency increases so does the impact of the sample clock jitter on a converter signal to noise ratio. Jitter is a specification important to converter clocks. Jitter is the variation of the clock edge in time, it is typically random and guassian distribution. In the case of an ADC the analog input frequency is sampled in time at the clock rising edge. If a very simple sinewave is input into a converter and its sample point varies due to jitter this will induce a random error. Also the clock has a wideband noise floor. This noise flloor could impact the noise floor of the ADC which reduces SNR.
Search the analog.com website for application notes AN501 and AN756. These application notes provide a lot of detailed information about this topic.
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