I have chosen the AD9524 for a new design, are there any common issues or problems I should be aware of to improve my chances of building a successful design the first time? Any other parts I should consider instead?

I have chosen the AD9524 for a new design, are there any common issues or problems I should be aware of to improve my chances of building a successful design the first time? Any other parts I should consider instead?

The AD9524 is very low noise and low power clock generator. It is a dual loop PLL which means it has 2 cascaded PLL integrated into 1 device. The first PLL uses a VCXO reference and a very narrow bandwidth (10Hz - 100Hz) that serves as a jiter cleaner to the reference. The second PLL multiplies the VCXO frequency to the VCO frequency and then is divided down to each of the 6 independent channel dividers.

A few considerations:

Since PLL2 serves as a frequency mulitplier the higher the VCXO frequency the less the PLL needs to multiply therefore the least noise that can be achieved.

The output drivers can be configured to either LVDS, LVPECL, HSTL or CMOS. The are not traditional LVPECL bipoloar drivers and do NOT require a pulldown resistor. Regardless of the mode, a 100 ohm differential resistor is required accros the outputs.

If the jitter cleaner function is not required the 1st PLL can be bypassed and the input reference can be driven into the OSC_IN inputs (single ended or differentially).

There is an appnote AN-1066 that gives a good description of power supply requirements and output to output coupling considerations.

The AD9524 is very low noise and low power clock generator. It is a dual loop PLL which means it has 2 cascaded PLL integrated into 1 device. The first PLL uses a VCXO reference and a very narrow bandwidth (10Hz - 100Hz) that serves as a jiter cleaner to the reference. The second PLL multiplies the VCXO frequency to the VCO frequency and then is divided down to each of the 6 independent channel dividers.

A few considerations:

Since PLL2 serves as a frequency mulitplier the higher the VCXO frequency the less the PLL needs to multiply therefore the least noise that can be achieved.

The output drivers can be configured to either LVDS, LVPECL, HSTL or CMOS. The are not traditional LVPECL bipoloar drivers and do NOT require a pulldown resistor. Regardless of the mode, a 100 ohm differential resistor is required accros the outputs.

If the jitter cleaner function is not required the 1st PLL can be bypassed and the input reference can be driven into the OSC_IN inputs (single ended or differentially).

There is an appnote AN-1066 that gives a good description of power supply requirements and output to output coupling considerations.