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AD9364 no-OS driver unable to complete initialization

Question asked by ravi@k2-inc.com on May 21, 2015
Latest reply on May 28, 2015 by DragosB

Hello Forum,

 

I am trying to bring-up ADI no-OS driver on my MCU for AD9364 using a 40 MHz crystal (XO into XTAL)

Following are the driver's default debug logs.

At the end of the debug, I am getting an MCU exception.

Before I looking into exception, can anyone analyze the logs and tell me if I am missing anything.

Thanks,

Ravi

 

ad9361_reset: by GPIO

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz

ad9361_setup

ad9361_set_dcxo_tune : coarse 8 fine 5920

ad9361_set_trx_clock_chain

ad9361_bbpll_set_rate: Rate 983040000 Hz Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_clk_factor_round_rate: Rate 245760000 Hz Parent Rate 3862640581 Hz

ad9361_clk_factor_set_rate: Rate 241415036 Hz Parent Rate 3862640581 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_clk_factor_round_rate: Rate 122880000 Hz Parent Rate 30176879 Hz

ad9361_clk_factor_set_rate: Rate 4294967274 Hz Parent Rate 30176879 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_clk_factor_round_rate: Rate 122880000 Hz Parent Rate 30176879 Hz

ad9361_clk_factor_set_rate: Rate 4294967274 Hz Parent Rate 30176879 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_clk_factor_round_rate: Rate 122880000 Hz Parent Rate 15088439 Hz

ad9361_clk_factor_set_rate: Rate 4294967274 Hz Parent Rate 15088439 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_clk_factor_round_rate: Rate 61440000 Hz Parent Rate 7544219 Hz

ad9361_clk_factor_set_rate: Rate 4294967274 Hz Parent Rate 7544219 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_clk_factor_round_rate: Rate 61440000 Hz Parent Rate 3772109 Hz

ad9361_clk_factor_set_rate: Rate 4294967274 Hz Parent Rate 3772109 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_clk_factor_round_rate: Rate 30720000 Hz Parent Rate 3772109 Hz

ad9361_clk_factor_set_rate: Rate 4294967274 Hz Parent Rate 3772109 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_clk_factor_round_rate: Rate 30720000 Hz Parent Rate 1886054 Hz

ad9361_clk_factor_set_rate: Rate 4294967274 Hz Parent Rate 1886054 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_clk_factor_round_rate: Rate 30720000 Hz Parent Rate 1886054 Hz

ad9361_clk_factor_set_rate: Rate 4294967274 Hz Parent Rate 1886054 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_clk_factor_round_rate: Rate 30720000 Hz Parent Rate 943027 Hz

ad9361_clk_factor_set_rate: Rate 4294967274 Hz Parent Rate 943027 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_rssi_setup

 

ad9361_auxadc_setup

ad9361_rf_port_setup : INPUT_SELECT 0x3

ad9361_pp_port_setup

ad9361_auxdac_setup

ad9361_auxdac_set DAC1 = 0 mV

ad9361_auxdac_set DAC2 = 0 mV

ad9361_auxadc_setup

ad9361_ctrl_outs_setup

ad9361_gpo_setup

ad9361_set_ref_clk_cycles : ref_clk_hz 40000000

ad9361_clk_factor_round_rate: Rate 40000000 Hz Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 40000000 Hz Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_clk_factor_round_rate: Rate 40000000 Hz Parent Rate 40000000 Hz

ad9361_clk_factor_set_rate: Rate 40000000 Hz Parent Rate 40000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_txrx_synth_cp_calib : ref_clk_hz 40000000 : is_tx 0

ad9361_txrx_synth_cp_calib : ref_clk_hz 40000000 : is_tx 1

ad9361_rfpll_set_rate: Rate 1200000000 Hz Parent Rate 80000000 Hz

ad9361_fastlock_prepare: RX Profile 0: Un-Prepare

ad9361_rfpll_vco_init : vco_freq 9600000000 : ref_clk 80000000 : range 2

ad9361_rfpll_vco_init : freq 9445 MHz : index 12

ad9361_load_gt: frequency 2400000000

ad9361_load_gt: frequency 2400000000 (band 1)

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 20000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_set_rate: Rate 1200000000 Hz Parent Rate 80000000 Hz

ad9361_fastlock_prepare: TX Profile 0: Un-Prepare

ad9361_rfpll_vco_init : vco_freq 9600000000 : ref_clk 80000000 : range 2

ad9361_rfpll_vco_init : freq 9445 MHz : index 12

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 20000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz

ad9361_load_mixer_gm_subtable

ad9361_gc_setup

Outcomes