I am trying to design a 50k Hz triangle ramp using ADF4518. The ramp bandwidth is around 200 kHz. I have attached my ADIsimPLL design. The simulation looks fine, but it can not be implemented. Please help me. Thank you very much.
What do you mean "it can not be implemented"? Are you using the ADF4158 evaluation boards? If you are, I recommend the attached settings.
Thank you for the reply. I am not using ADF4158 evaluation boards, but a real 24GHz radar system with ADF4158. Except the waveform, all the settings (reference frequency, loop filter etc) are fixed.
How are you programming the ADF4158? Are you able to get a fixed frequency output when you turn off the ramping?
We are using a commercial radar system and use microchip to program the ADF4158 through SPI. We can generate 100 Hz sawtooth with 75MHz bandwidth and 50 kHz FSK with step size as 600 kHz. Thanks.
Can you share the register settings you use for the 100 Hz sawtooth with 75 MHz bandwidth? I'll tweak those settings to get the waveform you want above.
Please provide your reference frequency too. I need it to decode the register settings.
I have attached our ADIsimPLL design for 100 Hz triangle waveform. The reference frequency is 30MHz. Please let me know if it is not enough for you. Thanks.
If you want to go from a 100 kHz step size to a 50 kHz step size, just reduce DEV_OFFSET by 1. This will half the frequency deviation.
Depending on the total ramp deviation you want, divide to total deviation by the step size to get number of steps to program (Register 6).
Is my original ADIsimPLL design for 50k Hz sawtooth correct? Thanks.
Your simulation shows 10 steps of 1.7 kHz. This gives a total ramp deviation of 17 kHz.
If you want 50 kHz steps, you need to increase the DEV and/or DEV_OFFSET values. DEV = 1398 and DEV_OFFSET = 2 gives 49.9964 kHz steps.
If you want a 200 kHz bandwidth, then you just need to set the number of steps to 4.
If you do this, the ramp times will be very fast. As a result, the loop won't be able to keep up with the ADF4158 output. I recommend slowing down the ramp (increasing CLK1 or CLK2) so the ramp isn't distorted.
Thank you for your help. The radar system has a prescalar with N = 16. That's why I set the ramp deviation as 17k Hz. We want the ramp change about 200k Hz in 0.01ms. Is this possible? What's the smallest number of steps I can set for a ramp? If I set the number of steps as 2 for an ramp, then what's the difference between this ramp and a two step FSK? Thank you very much.
Just to clarify some terms I'm using:
17 kHz deviation at 1.5 GHz = 272 kHz deviation at 24 GHz. One step in 0.01 ms is fine. It really depends on your loop filter. I know you can't change your loop filter component but you can increase your programmed charge pump current which will increase the loop bandwidth. I think this video will help your understanding a lot: http://www.analog.com/en/education/education-library/videos/1846356091001.html
You can have a ramp with ≧1 step. A 1 step ramp will be the same as FSK. The ADF4158 doesn't support 2 step FSK but a 2 step ramp would be the same as a 2 step FSK.
Is a N step ramp the same as a N step FSK? If this is the case, how to get the FMCW range equation? Does the ramp step voltage connect to an op amp integrator? Thank you very much.
There is no N step FSK. There is an FSK Ramp. Details attached.
If you are using a passive filter topology, the charge pump output goes into the loop filter. The loop filter changes the charge pump output current into a voltage which is connected to the VCO tuning pin.
If you are using an inverting active filter topology, the charge pump output goes into the loop fiilter's op amp. The loop filter's op amp inverts the signal and changes it to a voltage which is connected to the VCO tuning pin.
Is there any difference between ramp step and FSK step? In ADF4158 FSK Ramp slide 2, at which stage was the signal measured, before applied to vco or loop filter? How to get the measured signal? Thank you very much.
The FSK feature is designed so that you first lock the PLL at a certain center frequency. Then you set the frequency deviation; e.g. 100 kHz. Then, when FSK is enabled (R3 DB8), the output will be 100 kHz above or below the center frequency depending on if the TXdata pin is low or high.
For a ramp (R3, DB[11:10]) you lock the PLL to a certain center frequency. Then, after loading the ramp parameters in R4, R5, and R6, the output will step away from the center frequency until it hits the end of the sawtooth/triangle and then jump to the center frequency/step back to the center frequency; and repeat.
An FSK Ramp is a different feature to the two above. It is enabled with R5 DB25 and it described in the document above.
The measured signal was measured on an oscilloscope - time on the x-axis, voltage on the y-axis. It was measured at the VCO tuning pin input which is the same as the loop filter output.
Thank you for the reply. Can you give me some reference on the principle of step ramp? All my understanding are based on pure ramp. Can you help me to check my small triangle waveform design and let me know the problems. Thank you very much.
I think what you are calling a 'pure' ramp, is actually a stepped ramp but the steps are so small and so fast that it appears 'pure'.
If you slow down a ramp, by increasing the CLK1 and CLK2 values, you will see the ramp is actually made up of several small steps.You can experiment with this easily in ADIsimPLL.
Your triangle_100.pll looks good. If you want to more deeply understand what's going on, change:
This will give you the same end result but you will be able to see each step clearly. If may also help to increase CLK2 to make each step longer.
Attachments: ADF4158_8_step_sawtooth.png is a slow version of ADF4158_Ramp...Sawtooth.png.
Yes, 100Hz triangle works. How about the small triangle_50k.pll? Thank you very much.
That looks good too. It is about as fast as you can go. Any faster and the ramp shape will start to distort from a triangle.
I tried exactly same setting as yours, but I can not get the same result.
1. Time per ramp for up ramp is 2250 instead of 2000.
2. Time per ramp for second ramp is 250 instead of 0.
3. R3 value is 43 instead of 20043.
Can you post a screenshot of your measurement?
I tried to simulate ramp FSK with ADIsimPLL, but the second ramp dev does not look right to me. Is this because pre-scalar? Thanks
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