Where should I start when trying to diagnose the root cause of this problem?
There are a variety of causes of why a PLL will occasionally lose lock.
This answer assumes that the user is able to make their PLL lock, but it doens't stay locked.
The most common causes are:
1. Poor power and/or signal connections. Be sure that the part is properly soldered down, and that all connections are robust. Probe each pin with a voltmeter and use an oscilloscope to verify that the input signal is present and not violating datasheet specifications. Make sure that the input reference signal is not intermittant.
Many of ADI's older PLLs have the ability to use a status pin to view the reference divider ("R divider") output, and ADI's newer PLLs have an input freqeuncy monitor to verify that status of the input reference. Refer to the datasheet for more information.
2. Poor loop stability. This usually happens in analog PLL designs where the user has designed the loop filter and loop parameters for one input/output frequency combination and is using that design for a different frequency combination. Another common cause is changing the loop parameters (such as charge pump current) to increase/decrease the loop bandwidth. In both cases, the user should use ADIsimCLK to model their design and ensure that there is sufficient stability (at least 30 degrees of phase margin) for their operating point.
3. Noisy input reference signal. The lock detectors on the AD9516 and AD9520 families do a simple phase comparison, and it's possible that a very noisy reference signal may cause the instantaneous phase difference to be larger than the default value of 3.5 ns.
4. On the AD9510 and AD9511, there are cases where an anti-backlash pulse width larger than the default of 1.3ns may enable the digital lock detector to be more robust.
More information on these subjects can be found for the AD9516 and AD9520 families by referring to these user guides:
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