Question regarding how the ADC clock is set using the API. The API contains these functions ad9361_set_rx_sampling_freq and ad9361_set_rx_rf_bandwidth. The reference manual UG673 on page 10 says the ADC setup is accomplished using the set_rx_rf_bandwidth function. The set_rx_sampling_freq function does not appear to be referenced at all in this document.
My question is, is there a function to set the ADC clock to a desired frequency directly? If I want to configure an example similar to the LTE 10 MHz on page 36, where the ADC clock is 245.76 MHz and the ha digital halfband filters are used to decimate to 30.72 MHz rate, how do I use these functions? In this case is the "sample rate" considered to be 30.72 and the black box function set_rx_sampling_freq will configure the ADC clock and enable the appropriate halfbands? What if I wanted to alter this example to have the ADC clock be 122.88 and only enable 2 half bands? Does the API allow me to decide on the ADC clock itself and the decimation chain? It seems from this reference manual that the API is operating on a higher level and decides how to achieve the desired output sampling freq (after the digital filters). Would I need to operate below the provided API to do this?