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ADV7283- screen Issue with i.MX6

Question asked by kj.liu on May 19, 2015
Latest reply on Jun 2, 2015 by Rob.Analog

Hi Sir,

 

    My customer has a problem when using ADV7283 with i.MX6. As the following picture , the LCD has around 5 pixels gap in the top of screen no matter signal-end CVBS channel and Y/C(S-Video) channel, the gap all can't disappear. is there any suggestion to give us to fine tune this.we have check the pixclock is 27MHz(embedded bt656)

 

   The initial register setting is as below.

 

Autodetect_CVBS_Single_Ended_In_Ain_4_YPrPb_Out.py)

 

/* accesses main register space */

{ REG_ADI_CONTROL_1, 0x00},

/* delay 10 ms */

{ 0x0A, 0x00},

/* system functional(exit power down)*/

{ REG_POWER_MANAGEMENT, 0x00},

/* ADI required write(this is a hidden register !!) */

{ 0x52, 0xCD},

/* CVBS input on Ain 4(CCD)*/

{ REG_INPUT_CONTROL, 0x03},

/* ADI required write */

{ REG_ADI_CONTROL_1, 0x80},

/* reset clamp circuitry[step 1](this is a hidden register !!*/

{ 0x9c, 0x00},

/* reset clamp circuitry[step 1](this is a hidden register !!*/

{ 0x9c, 0xFF},

/* accesses main register space */

{ REG_ADI_CONTROL_1, 0x00},

/* ADI required write(this is a hidden register !!) */

{ 0x80, 0x51},

/* ADI required write(this is a hidden register !!) */

{ 0x81, 0x51},

/* ADI required write(this is a hidden register !!) */

{0x82, 0x68},

/* output drivers enabled */

{REG_OUTPUT_CONTROL, 0x0C},

/* outputs SFL information on the SFL pin, */

REG_EXTENDED_OUTPUT_CONTROL, 0x07},

/* SH1 C filter */

{REG_SHAPING_FILTER_CONTROL_1, 0x41,

/* LLC pin active */

{REG_ADI_CONTROL_2, 0x40},

/* accesses main register space */

{REG_ADI_CONTROL_1, 0x00},

pic1.jpg

pic2.jpg

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