I'm using several AD9958 DDS for generating multiple phase-synchronous sine-signals.
All DDS chips are receiving a 280MHz LVPECL clock via differential REF_CLK+/- inputs.
In order to provide phase-sync for all chips the SYNC_IN pins receive a 70MHz sync signal (LVCMOS 3.3V).
REF_CLK and SYNC_IN signals are provided by a clock generator and have exact phase relation.
Attached is a screenshot, depicting the signals (top to bottom):
- DDS SYNC_OUT, pin #2, which conects to annother chip, therefore the signal looks "loaded"
- DDS SYNC_IN, pin #1, supplied directly by the clock generator
- SYNC_CLK, pin #54, no load (except probe)
- I/O_UPDATE, pin #46, supplied by external logic in order to maintain setup/hold times
All signals were measured by 1K probes into 50R terminated scope inputs (2.5GHz BW) very close (within 3mm) to the DDS chip.
Unfortunately there is NO SETUP/HOLD time spec for the SYNC_IN signal to be found in the data sheet.
So I was guessing that the setup/hold spec for the SYNC_IN signal would be like the one for the I/O_UPDATE since (according to data sheet) both are oversampled by the DDS's internal SYNC_CLK - meaning min. 4.8ns setup- and 0ns hold- time.
As can be seen from the timing, my (green) SYNC_IN signal would comply to the 4.8ns/0ns setup/hold times, marked by the vertical marker lines, with respect to the DDS's own SYNC_CLK (blue). So far so good.
But if I would feed the DDS's own SYNC_OUT signal (yellow) into the SYNC_IN of the adjacent DDS, it probably would violate the setup/hold times, I was assuming above. Therefore my assumption of the (undefined) SYNC_IN setup/hold times being equal to the I/O_UPDATE setup/hold times can't be true - I reckon.
Would please someone comment if my thoughts are correct and - even more important - some ADI folks let me know what are the setup/hold times for the SYNC_IN signal with respect to the (DDS internal) SYNC_CLK ???
Thank's a lot in advance!