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Interrupt Vector Assignment and Interrupt Servicing Prioritazation.

Question asked by newbie on Mar 16, 2011
Latest reply on Mar 18, 2011 by PrasanthR



I am using BF 526 processor in my application. I am really confused about the SIC_IARx register and SIC_IMASK register. In my application i am using DMA3( SPORT0 RX) and DMA5(SPORT1 RX) in my application. I am not able to enable and get both of them to work together. I am sure it is some issue with my Interrupt  Assignment Register setting and SIC_IMASK setting. I am able to get both of them work individually. I read the HRM for BF52x...but its a little hard to understand.  Is there any document which explains how to do this :



"For general-purpose interrupts with multiple peripheral interrupts

assigned to them, take special care to ensure that software correctly

processes all pending interrupts sharing that input. Software is

responsible for prioritizing the shared interrupts. "



Please reply..Your help is really appreciated.

In BF526 both DMA3 and DMA5 share the same IVG9.... the same SIC_IAR2 and all..


can you please suggest some ways by which i can proceed ?