why I control 0channel output in the Schematic on sigmastudio，but when decode the signal ,the audio is output on channel5.So,I want to know how to deal this problem.
Register 0xE24C, The Other Pad Strength Register, bit 0 will increase the output strength of the CLKOUT. But, this may not the answer. Driving three parts may be too much to drive but I think it is probably more a signal integrity problem with reflections from poor terminations and vias and maybe too much capacitance. The only way to tell is by looking at the signal with a good active oscilloscope probe and or doing a simulation using Hyperlinx.
If you have poor terminations of this clock transmission line then increasing the CLKOUT drive strength will just make the ringing even worse.
So look for a message from me with for a private message.
Hello Mo j
Are you using TDM? Specifically TDM8?
If you have the LRCLK polarity set differently between the 1446 and other processors in the system you will get the signal for channel 1 show up on 5. You see the first four channels will be output when the LRCLK is low and channels 5-8 when it is high. If you switch to "DSP" or "Pulse" mode for LRCLK then it is customary for the start of a frame to be a positive going LRCLK pulse. So therefore channels 1-4 with the clock high. So a misconfiguration of the LR clock pulse can be easy to do. Note, when using TDM this is usually referred to as the Frame Clock.
So if you still cannot find the error then send over your SigmaStudio file and let me know what you are communicating to etc.
Thanks,Dave.You answer lest me know more.
I exactly used the tdm8 mode.But these is one point forgot to say.This problem occurs occasionally,sometime is nornal,sometime is error .So this problem make me trouble.Through your answer I know is the LRCK problem,but this unstable situation I do not know what causes ?What explains the change in status?
Thanks,this problem has been bothering me for a long time,the project now urgent ,hoping to find a solution.
Hello Mo j,
So sometimes it is correct and sometimes it is wrong?
Is it only when you turn it on or it is running correctly then suddenly snaps to the wrong channel?
What format of LRCLK are you using? Pulse or 50/50?
Since there is a delay in communication because of time zones I will make some guesses.
If you are using the pulse mode then I am assuming the pulse is one BCLK wide. This is a fairly short pulse so the signal integrity is important. In addition, should you have noise spikes on power or ground from other "aggressor nets" nearby then it can be seen as an LRCLK pulse and snap to the wrong channel. So take some scope plots of the LRCLK and on the same screen include the BCLK and Data. Give me some plots zoomed out so I can see the entire frame and then zoom in on the start of the frame so I can see about three or four BCLK cycles.
Then it may also be good to look at all the register settings when it is good and again when it is bad to see if any registers were changed.
I can also offer to look at your schematic and your layout and offer suggestions. If you do not want to share on a public forum then we can setup a private post for you to share those files.
Because this project is company confidential ,so i can't share on a public forum.
So how can i do to setup a private post to share these files.
Please forgive me.
These is my ADAU configuration.
Since this behavior differs between boards and is intermittent, check your PLL Loop filter components and their soldering. We have had similar issues caused by erratic PLL locking. Also be sure your uC is waiting long enough for the 1446's PLL to settle before loading its code.
I follow your ideas to test ,but i can not found error in PLL section.
now , I have three boards,the one control channel is normal.But the other two is error.One of them control channel is error(the 0channel-7channel and 16-19channel is normal,the 8channel-15channel is error，the8-11channel and 12-15channel has swap).
The other control channel is error(the 8channel-15channel and 16-19channel is normal,the 0channel-7channel is error，the0-3channel and 4-7channel has swap).
I want to konw how to deal this problem.You encountered such a situation? You is how to solve。
So take some scope plots of the LRCLK and on the same screen include the BCLK and Data. Give me some plots zoomed out so I can see the entire frame and then zoom in on the start of the frame so I can see about three or four BCLK cycles.
After that I will setup a private post so you can share the schematics and layout details.
I would like to ask if there are ways to increase the signal clkout. Problem now I know why, because the clock signal is not strong enough, causing a decoding error for CS4384.
I how to share my schematics and layout details,I can not find where uploaded.
Thank you for helping me all the way .
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