Is it possible to place a value of PLL_CTL in custom-register-reset-definitions section of the Custom Board support file? Will its settings actually change the core clock or not?
Witing for some resopnse.
Yes, you're right. In this case you can use the settings from VisualDSP++.
please don't try to do that. The emulation environment is not taking care about any programming sequence (cli, idle, sti) that is required when writing the MSEL bit field.
Is it ok to set the core clock and system clock through: "Project Options->Startup code settings->Processor clock and power settings->Custom Clock and Power Settings", for a multithreaded VDK application on custom board (for emulation as well as stand alone boot-from-flash operation)? Will any explicit settings to the EBIU registers needed in this case?
you can do it this way, but the settings are Evaluation Board specific. If you use e.g. a differnet CLKIN frequnecy you need some modifications. You're EBIU settings need to be calculatied according to the memory device data sheet and the system clock. Any settings done by VisualDSP++ are Evaluation Board specific.
So if I have a custom board whose CLKIN, RAM and Flash are all exactly the same as those on the BF537 EZKIT, then I should not have any problems in using those clock settings from the Visual DSP++. Right? (Well I have already successfully tested this thing, but just asking for a confirmation so that I don't get into some "unknown" issue due to this setting in future).
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