Hello,

I'm attempting to simulate the axi_ad9122 IP core in a testbench in vivado. I think I have it working pretty well and can get on with modifying the core, but a couple of questions.

my hardware setup is zedboard + adfmcomms1

1) In the **no-os drivers > dds_setup > dds_set_frequency**, i'm not quite understanding the calculation of the phase increment. I understand that for a dds the

**phase_increment = Frequency_out * 2^(n) / Fclk. (eq 0)**

Now the Fclk seems to be calculated as **clk_frequency * clk_ratio * 100000000 / 65536**. (eq1)

The clk_frequency and clk_ratio are read from the core registers, and the clk_ratio I understand. But my testbench (at a DCI of ~ 490 MHz, i.e. dac_div_clk of ~122 MHz ) seems to return a clk_frequency count of 4, and thats where I don't understand how this value can feed into eq1 to give the correct clk frequency. Please note that I am feeding into the HDL the exact same values as would've been configured in the software via dds_setup.

1) What is the factor 100000000 for in eq 1? Is it supposed to be multiples of 100 MHz?

2) What is the factor 65536 in eq1 ? Is this some sort of a 16 bit counter in the clock monitor module inside up_dac_common.v?

In conclusion I'd imagine this clk_frequency should come out to ~490 MHz so that the phase increment can be calculated as per eq 0.

Thanks for any comments on this.

Hi Omkar,

The interface clock frequency is relative to the processor clock, that in most of the cases it is 100 MHz. ADI_REG_CLK_FREQ is represented as unsigned 16.16 format, so this is the reason of dividing by 65536 (it is a shift by 16).

You can find more information regarding the HDL core registers on the wiki: http://wiki.analog.com/resources/fpga/docs/hdl/regmap#dac_common_axi_ad

Regards,

Dragos