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From ADC to BF561

Question asked by CyberSamu on Mar 10, 2011
Latest reply on Mar 22, 2011 by vinodbableshwar



I'm developing an application based on BF561.

I have an ADC connected to the BF561 through PPI0 interface. I have also a data ready signal connected to PPI0_FS1.

I'm using the PPI0 in the following mode:

PPI in Receive mode;

Non-ITU-R 656 mode;

1 external frame sync;

External trigger;

16 bits;

PPI samples data on rising edge;


My data ready is a burst signal with a max freq of some MHz.


I have 2 question:

which is the maximum frequency that the signal PPI0_FS1 can acquire?

when the BF561 gets the signal from PPI0_FS1, how many clk cycle the BF561 needs before a valid data is acquired?


or the data is immediatly available when the PPI0_FS1 ia asserted?


Thank you.