Where can find information about oscillator source for ADC and how change ADC sampling rate if external frequency source is used for MCU?
By default, the internal 10.24MHz PLL output is used as the clock source for the ADC.
This is divided by 20 to give a default ADC clock of 512kHz.
There is a low power option to divide the ADC clock down to 128kHz.
If you configure the part to change the UCLK source from the internal PLL output to an external clock source, you must take into account the clock divide ratio above.
I would caution you that we only charachterized the ADC performance using a 10.24MHz system clock source. If you use a slower clock, you will see a degradation in ADC performance.
For details on how to configure the ADC for different output rates, see the following thread:
Thank you for reply. So it is mistake in documetation about configuration frequency: ADCMDE.ADCCLKSEL (page 42)?
Set this bit to 1 to enable ADCCLK = 512 kHz. This bit should be set for normal ADC operation. Clear this bit to enable ADCCLK = 131 kHz. This bit should be cleared for low power ADC operation
It should read as follows:
"Set this bit to 1 to enable ADCCLK = 512 kHz. This bit should be set for normal ADC operation.Clear this bit to enable ADCCLK = 128 kHz. This bit should be cleared for low power ADC operation.
This is assuming UCLK = 10.24MHz"
Thank you - it is very helpful for me.
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