Lets say that the DSP core is being used for nothing other then data routing. In other words 1 stereo I2S input, being split into 4 stereo I2S output streams. Ergo no sampling frequency dependant filters are being used.
Lets say the DSP is set to generate the start pulse based off of the sampling frequency present on the input clock domain. Lets say it starts up at 48khz. The chips intput/outputs are also slaved to this same clock domain.
If the sampling frequency were to now change to 96/192khz would this require a reset of the chip or would it adapt to the new sampling frequency?
Obviously the ADAU144x isn't working as a master for any of the clock domains, so no software changes are required to reflect the change of the input sampling frequency, the BIT and LR clocks are provided by another source.
Initially I thought that I'd have to reset the ADAU144x when the sampling frequency changed, so that the core would start up from the new sampling frequency present on the intput clock domain. However when going about this I noticed that the rate of the data stream being output changed to reflect the rate of the data stream on the input, without needing to pass a reset.
Do I need to reset the chip when the sampling frequency changes or can the chip handle this itself? Obviously I'd need to change the software if filters were being used, but if they aren't?