I can see in the datasheet of AD9857, in the Ref Clock input characteristics, the Differential Input levels. But:
What about if the input is single? What are the levels for the Ref Clock input?
MAg - Not obsolete yet, but certainly not new. The AD9957 is a newer version device with much the same functionality. take a look at that instead.
Sorry for the delay. When pin 60 is grounded, I believe the REF CLK (pin 62) accepts 3.3V CMOS logic levels, but I need to check on that. I reply back ASAP.
Do you already know it ?
The designer emailed back he's having issues opening up the now "old AD9857 project file" to veiw.
The part is over 10 years old. He also having a new part tape this Friday, so his priority is to meet that dead line. I will continue to press. I hope to know something by the end of the week. Your patience has been much appreciated. Sorry for the inconvenience.
AD9857ASTZ is 10 years old? my god I am using obsolete technology? Do you propose me another DAC?
We are using AD9857, so do u know the levels i asked?
The designer is having issues downloading the files to run simulations. The CAD department thought they had it fixed for the designer yesterday but problems still persist. Hopefully soon. I apologize for the delayed response. As soon as I here something I'll post ASAP.
I finally got the answer, sorry it took so long. If the AD9857 is setup for single ended REF CLK mode via pin 60, then the REF CLK goes thru a CMOS circuitry. So, the REF CLK should meet CMOS levels. e.g. the min logic high is 2.0V and the max logic low is 0.8V.
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