When reading from any of the AD719x products only the first read after power-up is successful.
All subsequent read operations give invalid results. What could be happening?
It is probable that the digital interface is entering an unexpected state following the read operation. When using the digital interface of the AD719x, it is critical that the correct number of clock cycles is provided when reading from or writing to the control registers. If one extra clock cycle is provided and a write operation is then attempted, the part will enter an unexpected state. Similarly, if less than 16 clocks are provided when reading from a 16-bit register, the interface will lose synchronization.
Another probable cause is spurious clocks on the SCLK line. The first bit of any write to the communications register is a zero. The ADC will ignore bus activity until it receives a zero. If DIN is left low after performing a read, any spurious clocks on the SCLK line will clock a bit into the communications register. The next time that eight bits are written to the communications register, only the first seven bits will be loaded and the eighth bit will be interpreted as the first bit of a subsequent write. This problem can be avoided by pulling DIN high after each write.
If the /CS line is being used as a Frame Synchronization signal, ensure that this line is brought high at the correct time. Also ensure that the correct number of clock pulses have occurred before /CS is brought high.
If the interface does lose synchronization, writing 40 1s into the device will reset the interface and the on-chip registers to their power on values.
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