How does switching between channels affect throughput of the AD719x devices.
The output data rate, which is listed in the datasheet, is the rate at which valid conversions are available when continuous conversions are being performed on a single channel. When the user switches to another channel, additional time is required for the sigma delta modulator and digital filter to settle. The settling time associated with these converters is the time it takes the output data to reflect the input voltage following a channel change. To accurately reflect the analog input following a channel change, the digital filter must be flushed of all data pertaining to the previous analog input.
The AD719x has several filter options. The filter option selected determines the range of output data rates that are available. The filter also determines the settling time which is the time required to generate a fully settled conversion following a channel change. For example, if the sinc4 filter is selected and chop is disabled, it takes four times the programmed output data rate (conversion time) to clear the filter. Therefore, if the output data rate is 50 Hz, for example, the time required to generate a valid conversion after switching channels is (1/(4*50 Hz)) = 80 ms. Application note AN-1084 discusses the different filter options available on the AD719x family. It also lists the available output data rates, the settling time and the maximum number of channels that can be converted per second for each filter type (throughput).
When a channel change occurs, the digital filter and modulator are automatically reset, /RDY goes high and will remain high until a valid conversion is available from the ‘new’ analog input channel. Therefore, following a channel change, /RDY will remain high until the digital filter has calculated a valid conversion.
When a step change occurs (on the analog input channel being converted), the ADC is not reset. The ADC continues to output conversions and /RDY continues to pulse when a conversion is valid. However, the conversions will not be valid as the digital filter will require the complete settling time to generate a digital word relevant to the altered analog input. Again using the sinc4 filter/chop disabled example, the ADC will output a valid word 4 conversion cycles later if the step change occurs at the beginning of a conversion cycle. However, if the step change occurs asynchronously so that it occurs in the middle of a conversion, the ADC needs to complete the present conversion and then perform 4 more conversions to generate an output valid to the ‘new’ analog input. Therefore, it may take 5 conversion cycles from the instant at which the step change occurs to the instant at which a valid conversion is available.
In summary, the channel switching speed is dependent on the settling time which is dependent on the filter type selected.
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