AnsweredAssumed Answered

AD9889B with internal syncs

Question asked by HankZ on Feb 25, 2011
Latest reply on Mar 2, 2011 by Matt.M

I am having issues setting up the AD9889B to utilize 20 bit 4:2:2 YCrCb data with embedded syncs.

The problem is that the part does not seem to recognize the video format (480i); register 0x3e and 0x3f simply returns 0x00.

My setup is using video ID 2 (4:2:2, YCrCb with embedded syncs 1x pixel clock) and style 3 combined with 10 bit (resulting in a 20 bit bus).

He’s running 480i with a 20 bit bus uses a pixel clock of 13.5 mhz; Note here that their monitor in the lab has a DVI input, so the engineer has the AD9889B setup in DVI mode.

I have reviewed the programming guide at length, but have not found a particular register that fixes his issue.

My questions are as follows:

1.     Are there any restrictions on using Bt.656 style input data with embedded syncs ? 
2.     Will the AD9889B accept data containing embedded audio or ancillary data even if in DVI mode ?

I was hopeing the part would ignore the extra data since it is during the blanking interval, but still sync to it.

I was able to get the system working, but only when I switched to using the external H, V and DE inputs.  The data still had the embedded syncs present.

Thanks in advance for any guidance you can provide.

Outcomes