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FPGA - PPI timing related

Question asked by rifo on Feb 24, 2011
Latest reply on Mar 12, 2013 by CraigG

Hello all,

 

I am working on an interface between an FPGA and BF537 via PPI. I have almost finished the design but have some doubts related to PPI timing. I would be most happy if you can check the PPI_rx & PPI_tx timing diagrams that I have drawn and comment on any missing / wrong stuff. Note that all the signals in the timing diagram are created in the FPGA. There are also some comments in the figures like "drive_data0, fsync1_sampled". They refer to what happens in the Blackfin PPI at that instant.

 

I have my doubts especially regarding the;

 

1) 1.5 PPI_clk mandatory delay in PPI_tx side

2) fsync1 and data0 alignment in the PPI_rx side

 

 

thank you very much for your time

cheers

rifat

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