I have a problem communicating with the chip. Logic Analyzer indicates nice read/write packets but I get zero when I try to read from the chip.
May be my SPI mode is wrong? Currently it’s - Clock idle low, sample on falling edge.
From the plots you have provided, it looks like /SYNC ("Channel 1" in your plots) is not coming low until after the 4th SCLK ("Channel 2") pulse. The AD5421 is 24 bits wide (or 32 if CRC error checking is required). The input shift register consists of 8-bit address/command byte and a 16 bit data-word.
When /SYNC is low, data is transferred on the falling edge of SCLK. The input shift register data is latched on the rising edge of /SYNC.
SYNC line is Channel3 - SPI-ENABLE. Channel 1 is SPI-MISO - SDO pin of the chip.
Retrieving data ...