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AD7626 Interface Question

Question asked by ClaireL Employee on Feb 22, 2011
Latest reply on Feb 22, 2011 by ClaireL
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I am designing an interface to the AD7626 from an FPGA using the echoed-clock mode and running at the maximum sample rate of 10 MSPS.  Please refer to figure 2 on page 6 of the datasheet for this question.  I am confused by the timing and how I can achieve tMSB and tCLKL while still maintaining the full 100ns timing btween CNV pulses.

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