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ADuC7061 slave SPI, 20 uS delay between byte transfer.

Question asked by olegmsg on Feb 18, 2011
Latest reply on Feb 20, 2011 by MMA

I have ADuC7061, 10.24 MHz clock (UCLK) for the system.
Programming SPI interface in polling mode, slave, one byte transfer.
SCLK from master - 2MHz, master set low CS for every byte - according to Figure 5 Page 12 ADuC7061 Datasheet.
In polling mode CPU check SPISTA BIT0 (or BIT6, or BIT8 - one byte transfer).
And I have to insert 20 uS delay on the Master side between byte transfer.
Otherwise ADuC7061 losing bytes.
Here is ADuC7061 polling mode program fragment:

 

while (n < N){


      SPIMSTATUS = SPISTA;

 

     //////if ((SPIMSTATUS & BIT0) == BIT0){

     //////if ((SPIMSTATUS & BIT6) == BIT6){

     if ((SPIMSTATUS & BIT8) == BIT8){

          .........

          MESSAGE[n] = SPIRX;

          .........

          n++;

     }
                                   

}

 

20 uS delay on the Master side between byte transfer. Is it correct?
What about 3 - 5 uS?

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