we are using ADS9833 as clock synthesizer with MCLK input of 25MHz. We need to generate frequency around the value of 3.6864MHz. What we see is that the signal generated is bad, with 40ns jitter on clock period. This value is indipendent from frequency value output (we try to set frequency up to 12.5 MHz). I would have expected a jitter value compatible with the MCLK input jitter (or even less).
Because the jitter value is equal to MCLK input clock period, my questions is:
- This jitter value is typical for this DDS with this MCLK input? (In the preliminary release of datasheet I seen that the jitter declared is 100ps... value that disappear in the document final release)
- Is there anything that we can do to eliminate or drastically reduce this jitter value?
- Is there other DDS solution in ADI portfolio with low jitter clock synthesis?
Thank you for your help!