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AD9956 Lock Problem

Question asked by BenjaminHo on Feb 15, 2011
Latest reply on Aug 18, 2011 by DSB

I need to sweep 30.46875 MHz to 35.15625 MHz in 2ms or less. Is the AD9956 able to support? If yes, what is the recommended RDFTW and RSRR and PS0 rate.

Case 1 :

32.03125 MHz to 35.15625 MHz (Bandwidth 3.125 MHz) look fine

 

Case 2 and Case 3 all settings are the same except the sweep range. Case 2 = 32.8125 MHz to 34.375 MHz and Case 3 = 30.46875 MHz to 32.03125 MHz. They have same bandwidth.

 

Rising Delta Frequency is 0.0015625 MHz, Ramp Up Step Interval is 2us, Linear Sweep Enable set, Linear Sweep No Dwell set, Serial I/O mode is 3 wire, PLL Lock Detect Enable set. System Clock is 200 MHz, PS0 ‘s period is 2ms.

 

You can see from the green line Case 2 go high only (unlock) when going from High Freq to Low Freq whereas Case 3 is a bunch of green lines even Vtune is sweeping correcting.

 

kindly advise what is the possible cause of case 2& case3

 

 

Q:

If I don’t want to use the PLL in the AD9956, how should I terminate the unuse pins?

Should I tie the unused input(PLLREF/PLL OSC) through a 100 pF capacitor to the analog supply (AVDD).

 

Message was edited by: BenjaminHo

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