When the CPU clock is selected at 41.78MHz, the ADC can randomly return extremely large values. But when we set the CPU clock at 20.89MHz, we can not see this issue again. Can you explain the reason for this?
Firstly, the ADuC702x ADC is limited to 1MSPS sampling rate.
My suspicion on this issue is that a sampling rate of greater than 1MSPS is used.
The ADC sampling rate is related to the CPU clock – fADC = 41.78MHz/CD value.
Check the ADCCON register.
This thread on the forum should be helpful.
The ADC block is clocked by the system clock as selected via PLLCON[1:0].
By default this is the 41.78MHz PLL output but, it could be an external clock applied to P0.7.
ADCCON[12:10] bits select the divide rate for the system clock to the ADC.
The overall ADC sampling frequency of fadc/ADCCON[12:10]/ 19+#Acq.clocks
1MSPS is the maximum specification.
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