I want to implement a PLL lock with the PFD frequency >50 MHz. I'm currently using the ADF4007 and this works great, but because the RF input has a minimum divider of 8, I can only input frequencies larger than 400 MHz. I want to be able to lock RF input signals from 200 MHz (ideally 100 MHz). I was looking at the ADF4002 as this lets me use a prescalar divider of 1, so I could lock down to 50 MHz. But the ADF4002 only allows RF input frequencies up to 400 MHz, and I need to go up to 5 GHz, which the ADF4007 can do.
Anyone have a good idea on how combine the frequency range of these two chips? If I could find a divider that has an input stage like the ADF4007 where I could adjust the divide by from 1 or 2 up to 64, that would be ideal as that output could go to the ADF4002.