I'm running a BF-526 on the EZBRD. I have the SPI running in RDBR_CORE mode. I've attached the code, along with screen captures of the logicsignals. I have the SPI interrupt set up to read from the RDBR register to initiate transfer. If you look at the not_working.jpg screen capture, the YELLOW test line toggles high and then low really quickly, indicating that every second interrupt is happening before the SPI is done receiving data. But since I have the SPI running on the RDBR_CORE mode, it should only interupt when new RDBR data is ready to be read. You'll see in my code I have a commented out if statement checking the RXS bit. If you uncomment that, everything works fine, as shown in working.jpg.
I'm noticing when I look at SPI_STAT right now an interrupt occurs, that half the time the RXS is not set, but the TXS is. So is the TXS bit somehow causing the interrupt to happen?
Any help on this would be appreciated.