we are using ADF4350 to generate 500MHz clock.but the problem what we are facing is that the pll is not getting locked and if we program for 500Mhz, the clock it is generating is 470MHz(in this case also PLL is not locked). and if we program it for some other frequency we are not getting any output.
We throughly checked the programing data and timing every thing is perfect.
We are suspecting in the placement of Loop filter components
I wanted to know know like whether the placement of capacitors and resistors of loop filter will affect the clock generation.?? and if it does then how ?
we checked in the evaluation board the voltage across the capacitors of loop filter are changing depennding on the frequency we program. But in our case it is remaining constant.We are not able to understand what the problem is .
I am attaching the schematic of the synthesiser. let me know if there is any thing wrong in that and any advice on loop filter....and regarding its placement.
Thanks and regrads,