AnsweredAssumed Answered

Several questions about ADAU1442

Question asked by BiancoZandbergen on Jan 31, 2011
Latest reply on Feb 17, 2011 by BrettG

Hello,

 

I have a few questions about the ADAU1442:

 

1. Do any of the following pins have pullup resistors:

 

ADDR0
ADDR1
SELFBOOT
CLKMODE0
CLKMODE1
PLL0
PLL1
PLL2
RESET

 

When I look at the evaluation board schematics ( www.analog.com/static/imported-files/user_guides/UG-032.pdf )
I'm pretty sure that all the pins except RESET have internal pullups because a dipswitch is used to connect them to ground, however this is not decribed in the datasheet and i would like to know for sure.

 

2. is the output of the external clock (in buffered oscillator configuration) dependent of the state of the reset pin?
i.e. is there still an external clock when the oscillator is running and the reset pin is pulled low?

 

3. When using a serial output port in slave mode, what happens when data is not clocked out within time? How does the master on the other side knows that the SigmaDSP is ready to start sending the audio stream?

 

4. When I look at Table 20. Master Mode Clock Domain Assignment on page 34 of the datasheet and compare it with the pinout i notice the following:
The BCLK, LRCLK and SDATA_IN pins are next to each other in each pair. However all the SDATA_OUT pins are seperated from the respective BCLK and LRCLK pins.

 

For example take clock domain 1, an exclusive input port:
LRCLK1: pin 10
BCLK1: pin 9
SATA_IN1: pin 8

 

Clock domain 4 set as input port:
LRCLK4 : pin 97
BCLK4    pin 96
SDATA_IN4: pin 95

 

Clock domain 4 set as output port:
LRCLK4 : pin 97
BCLK4    pin 96
SDATA_IN4: pin 79

 

Clock domain 9, an exclusive output port:
LRCLK9: pin 71
BCLK9: pin 70
SATA_OUT0: pin 98

 

Are my observations correct? This would mean that output ports are less easy to route on a PCB.

 

5. How to put the SigmaDSP in SPI mode? There are several references in the datasheet to SPI mode however it is not explained how to actually put the device in SPI mode.

 

6. The evaluation board uses a ADM811 to generate the reset signal. This chip has a minimum reset delay of 140ms after the power supply is within specifications. Is such a long delay neccesary? Do we have to wait till the PLL has locked before pulling up the reset? In that case how do we know that the PLL has locked other than using a large enough delay to be safe? The minimum PLL lock time is not specified in the datasheet as far as i can see.

Outcomes