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max bandwidth for an fpga on async bank

Question asked by rifo on Jan 30, 2011



I am planning to interface bf537 with an fpga (spartan 6) via ebui's async bus controller.  This is my first attempt with an async bus and there are two points that I am not clear. I would be most happy if you can guide me about them.


1) If I want to have consecutive writes, do I have to code for the setup, hold cycles in the fpga for every data to be written. I have read the hardware reference and got the impression that this is the case. If this so then the can I calculate the bandwidth as

           ( F_sclk / (setup+write+hold) ) * 16  bits/second.

I have thought that, the setup+write+hold access would be there only for the initial data and then as long as I kept AMS and AWE low, I can write one data per sclk cycle.


2) In the hardware reference, there is an example connection for an SRAM on the async bus. ARE pin is left unconnected and the read access is managed by AOE pin alone. Am I correct in assuming that the "read access" definition on page 6-20 in hardware reference automatically becomes

read access: the time between read-enable assertion (AOE low) and deassertion (AOE high).


note that I have replaced the ARE in the original definition with AOE.


thank you very much for your time