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SPORT TX interrupt issues

Question asked by 2sb18 on Jan 27, 2011
Latest reply on Feb 7, 2011 by Prashant

Hi All,

 

I've been playing around with the SPORT on tehe BF526-EZBRD. I have a couple problems/questions. I've included the pertinent code below.

 

1) How do you get the SPORT TX interrupt to trip. In the Processor Hardware Reference, it states that an interrupt will occur once you set the TSPEN bit, but it doesn't seem to be happening in my case. I can get the RX interrupt to occur, by setting the RSPEN bit.

 

2) How do you deassert the SPORT interrupt? I thought it would be something like reading my SPORT_RX or writing to SPORT_TX. It seems my isr_codec function is continually running.

 

Thanks for the help!

 

Steve.

 

 

 

EX_INTERRUPT_HANDLER ( isr_codec ) {
     // workaround for anomaly 05000473 - interrupted SPORT receive data register read results in
     // underflow when SLEN > 15.
     int temp_SIC_ISR = * pSIC_ISR0;
     int temp_IMASK;
     temp_IMASK = cli();
     int RX_DATA = *pSPORT0_RX;
     * pSPORT0_TX   = 100;
     sti ( temp_IMASK );
}
int main ( void ) {

     // configuring the SPORT interrupt
     *pSIC_IMASK0 |= 0x100;     // SPORT0 has a peripheral ID of 8.
     register_handler ( ik_ivg7, isr_codec );
     // configuring ports
     * pPORTG_FER = 0x87C0;
     * pPORTG_MUX = 0x0150;
     // SPORT configuration
     * pSPORT0_TCLKDIV = 100;
     * pSPORT0_RCLKDIV = 100;
     * pSPORT0_TFSDIV = 4;
     * pSPORT0_RFSDIV = 4;
     * pSPORT0_RCR2 = SLEN ( 23 ) |  // SPORT RX Word Length is 24
                         RSFSE;               // RX Stereo Frame Sync Enable
     * pSPORT0_RCR1 = RFSR |          // Receive Frame Sync Required Select
                         RCKFE |          // sample on rising edge
                         ITCLK |          // generating the clocks
                         ITFS;
     * pSPORT0_TCR2 = SLEN ( 23 ) | 
                      TSFSE;
     * pSPORT0_TCR1 = TFSR |
                    TCKFE |
                    IRCLK |
                    IRFS;
     * pSPORT0_TCR1 |= TSPEN;          
     * pSPORT0_RCR1 |= RSPEN;          // enabling
     while ( 1 ) {
     }
}

 

Message was edited by: 2sb18

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